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MicroVAX 78032 : ウィキペディア英語版
MicroVAX 78032

The MicroVAX 78032 (otherwise known as the DC333) is a microprocessor developed and fabricated by Digital Equipment Corporation (DEC) that implemented a subset of the VAX instruction set architecture (ISA). The 78032 was used exclusively in DEC's VAX-based systems, starting with the MicroVAX II in 1985. When clocked at a frequency of 5 MHz, the 78032's integer performance is comparable to the VAX-11/780 superminicomputer, which was introduced on 25 October 1977. The microprocessor could be paired with the MicroVAX 78132 floating point accelerator for improved floating point performance.

The 78032 represented a number of firsts for DEC. It was DEC's first single-chip microprocessor implementation of the VAX ISA and DEC's first self-fabricated microprocessor. The MicroVAX 78032 is also notable as it was the first semiconductor device to be registered for protection under the Semiconductor Chip Protection Act of 1984.
The MicroVAX 78032 contains 125,000 transistors on an 8.7 by 8.6 mm (74.82 mm2) die that was fabricated in DEC's ZMOS process, a 3.0 µm NMOS logic process with two layers of aluminum interconnect. The die is packaged in a 68-pin surface-mounted leaded chip carrier.
==MicroVAX 78132==

The MicroVAX 78132 (otherwise known as the DC337) is a floating-point coprocessor for the MicroVAX 78032 microprocessor. It interfaces to the MicroVAX 78032 via the DAL bus and a few control lines. The MicroVAX 78132 was responsible for executing 61 out of 70 floating-point instructions defined by the MicroVAX subset of the VAX ISA and accelerates nine integer instructions.
The MicroVAX 78132 has a 100 ns microcycle divided into four 25 ns clock phases which is generated by a 40 MHz input clock. It was composed of five "elements": a 67-bit fraction processor, a 13-bit exponent processor, a 1-bit sign processor, a microsequencer and a bus interface unit.
The MicroVAX 78132 contained 32,141 transistors on a die measuring 8.4 mm by 6.6 mm (55.44 mm2). It was fabricated in DEC's ZMOS process, a 3.0 µm NMOS process with two layers of aluminum interconnect; and is packaged in a 68-pin surface-mounted leaded chip carrier.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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